Should i enable apic

Ask Question. Asked 12 years, 1 month ago. Active 8 months ago. Viewed k times. Improve this question. Abtin Forouzandeh Abtin Forouzandeh 1, 3 3 gold badges 12 12 silver badges 13 13 bronze badges. Add a comment.

Active Oldest Votes. Improve this answer. Anthony Mastrean 1 1 gold badge 6 6 silver badges 18 18 bronze badges. Goyuix Goyuix 3, 5 5 gold badges 27 27 silver badges 36 36 bronze badges. Can you explain the last paragraph? What is the benefit of turning off ACPI? MatthewFlaschen: you took the words out of my mind. Nic Nic The total number of usable interrupts climbs from 16 to In addition, interrupt handling becomes noticeably more flexible, while also leading to time savings in data management.

In this mode of operation, pairs of devices can exchange data especially quickly, because multiple data transfers can be initiated or acknowledged with a single signal instead of requiring each individual item to be handled or acknowledged separately.

You should also test the system thoroughly for stability after making such a change. Students Click Here. What is this mode and should I enable it?

Thanks all :. Advanced Programmable Interrupt Controller just do a google search and should find plenty of information on it, put in your OS version and may find more related to what you want to know. My error, sorry.

Its used in multiprocessor systems. Note: I don't think you can move it any further than the 4th Gb. The correct value for this field is the IRQ number that you want to map the spurious interrupts to within the lowest 8 bits, and the 8th bit set to 1 to actually enable the APIC see the specification for more details.

You should choose an interrupt number that has its lowest 4 bits set and is above 32 as you might guess ; easiest is to use 0xFF. This is important on some older processors because the lowest 4 bits for this value must be set to 1 on these.

Disable the PIC properly. This is nearly as important as setting up the APIC. You do this in two steps: masking all interrupts and remapping the IRQs. Masking all interrupts disables them in the PIC. Remapping is what you probably already did when you used the PIC: you want interrupt requests to start at 32 instead of 0 to avoid conflicts with the exceptions.

You should then avoid using these interrupt vectors for other purposes. This is necessary because even though you masked all interrupts on the PIC, it could still give out spurious interrupts which will then be misinterpreted from your kernel as exceptions. In original architecture, the APIC could not be mapped to memory, and it wasn't until later changes that it became mappable. The result of this is that SMM memory is pushed outside its protected range and exposed to lesser-privileged permission rings.

Using this method, attackers can leverage their permissions using System Management Mode, which is protected from all rings above In newer generation Intel processors starting with the Intel Atom in , this has been taken into account. However , this relies on the SMRR to be configured correctly. Otherwise, this mitigation will not work properly and attackers will still be able to use the attack.

Make sure you map these to virtual memory if you are using paging. Each register is 32 bits long, and expects to be written and read as a 32 bit integer. Although each register is 4 bytes, they are all aligned on a 16 byte boundary. Write to the register with offset 0xB0 using the value 0 to signal an end of interrupt.